A typical charge trapping dielectric flash electrically erasable and programmable memory device can be manufactured on a semiconductor substrate having a core area and a periphery area. The memory device can include a core region containing an array of double-bit memory cells and a periphery region containing logic circuitry, such as MOSFETs (metal oxide semiconductor field effect transistors). A typical array of double-bit memory cells in the core region can include, for example, 512 rows and 512 columns of double-bit memory cells. The MOSFETs in the periphery region typically are designed for use in programming and erase operations in conjunction with the double-bit memory cells. The different devices formed within the core and periphery regions can have different functional and performance requirements and, therefore, different structural features.
A pervasive trend in modern circuit manufacture is to downscale device size in order to achieve higher density circuits, while still maintaining or enhancing desirable device properties and performance. In addition, where possible, it is advantageous to form or otherwise fabricate simultaneously the core memory devices and the periphery logic devices.
However, problems may exist with the simultaneous fabrication of core and periphery devices. Processing associated with structures on one side of the device (e.g., in the periphery region) may have an adverse effect on structures on the other side of the device (e.g., in the core region). For example, in one conventional fabrication process, bitlines, which serve as source and drain regions for the memory cells, are implanted or otherwise formed in the core region, followed by formation of gate dielectric layers in the periphery region. While this fabrication methodology may provide some advantages, distinct disadvantages exist. For example, problems may exist with respect to lateral bitline diffusion in response to thermal processing associated with the formation of gate dielectric layers in the periphery region.
This lateral bitline diffusion can further reduce the channel length of the memory cells in the core region and alter the abruptness of the source/drain junctions. Due to device downscaling, memory cells are already fabricated with an active channel region having a relatively short channel length. As the physical dimensions of memory cells decrease, this process-associated reduction in channel length, taken in conjunction with processing measures already in place to reduce feature size, can lead to short channel effects (SCE) in the memory cells of the memory device. SCE can cause threshold voltage skews at the channel edges as well as excessive sub-threshold currents (e.g., punch-through and drain induced barrier lowering (DIBL)).
One solution to the problem of lateral bitline diffusion has been to reduce the thermal processing associated with the formation of the gate dielectric layer(s) in the periphery region. However, doing so results in degraded gate dielectric layers in the periphery devices, which is also highly undesirable.
Accordingly, there is a need in the art for improved methods of fabricating memory devices, such as charge trapping dielectric flash memory devices, which are both efficient and effective for producing downscaled devices.